The detection of radar signals in strong and varying clutter requires signal processing capabilities with the combination of high speed and a very wide dynamic range. The dynamic range is determined by the system noise level with which the signal is quantized. The analog-to-digital (A/D) converter is a critical part of the signal processing apparatus and is crucial to the achievement of linear dynamic response required for clutter cancellation. The current state-of-the-art high-speed high-resolution analog to digital converter suitable for airborne radar application is 14 bits at a 5 MHz sampling rate. The architecture of a conventional, prior art subranging A/D converter is shown schematically in FIG. 1 for an N-bit converter.
In this scheme, as shown in the figure, a conversion is performed in two successive stages with three functional blocks and two converter blocks. The input signal is sampled and held constant by a sample-and-hold (S/H) circuit. The output of the sample-and-hold circuit is applied to both a flash encoder, ADC1, in converter stage 1, and a subtraction circuit in converter stage 2. The output of the first flash encoder is then fed to a digital-to-analog (D/A) converter to obtain an initial approximation of the input signal, which is also applied to the subtraction circuit. The subtraction circuit in converter stage 2, which is formed from amplifier AMP3 and several resistors, produces an error signal derived by subtracting the approximated signal from the original sample signal. The amplified error signal is then applied to a second flash encoder, ADC2, in converter stage 2. The outputs of the first and second encoders are combined by a digital error correction unit to determine the final N-bit word. The amplifier AMP1 shown in FIG. 1 is the input buffer which usually has unity gain and it isolates the input from the rest of the circuit. During the sample mode, the switch is closed and capacitor C charges up to the input signal voltage. When the converter enters the hold mode, the switch opens, and the capacitor voltage maintains a constant value. Output buffer amplifier AMP2 provides a duplicate of the voltage on the hold capacitor. It should have a very high input impedance to avoid loading the capacitor. The entire circuit from AMP1 to AMP2 is referred to as the sample-and-hold (S/H) circuit. In the analysis to follow we assume that this switch is a diode bridge since this is what is used in most S/H circuits.
Stage 1: The flash converter, ADC1, makes a coarse digitization of the signal to a resolution of M bits. The digital word from ADC1 is applied to a very fast reconstruction digital to analog converter that produces an output current equal to and of opposite sign from the current flowing through resistor R2. The resolution M of ADC1 is one bit more than half of N, the total A/D converter resolution.
Stage 2: The error amplifier, AMP3, is an operational amplifier with feedback that holds the amplifier input near ground potential, so the current in R2 is proportional to the sample and hold output. The difference between the R2 current and the digital to analog converter output current represents the error in the stage 1 measurement. This difference current flows through resistor R3. A second A/D converter, ADC2, measures this error voltage. The two A/D converters must have a total resolution of at least one or two bits greater than the final system in order to allow error correction. The error correction circuit prevents the noise and errors of ADC1 from appearing in the final output; however, ADC2 will contribute noise.
Thirty-five percent of the total internal noise for the currently available 14-bit 5 MHz A/D converter comes from the S/H and fifty-one percent comes from ADC2. Current A/D converters are also limited by the technology to ten bits as the number of bits used for the first and second flash stages. It is therefore desirable to increase the accuracy of the second converter stage without increasing the resolution of a flash converter. An architecture for A/D conversion that overcomes the limitations of the current state-of-the-art must decrease the noise due to the S/H and fine quantization circuit while maintaining high digital word resolution.